Modern time-of-flight (TOF) systems can ascertain depth distances Z to a target object by emitting modulated optical energy of a known phase, and examining phase-shift in the optical signal reflected from the target object, the phase-shift being detected by an array that includes pixel detectors and their dedicated electronics, collectively an array of “pixels”. Exemplary such phase-type TOF systems are described in several U.S. patents herein. These patents include by way of example U.S. Pat. Nos. 6,515,740 “Methods for CMOS-Compatible Three-Dimensional Imaging Sensing Using Quantum Efficiency Modulation”, 6,906,793 entitled Methods and Devices for Charge Management for Three Dimensional Sensing, 6,678,039 “Method and System to Enhance Dynamic Range Conversion Useable With CMOS Three-Dimensional Imaging”, 6,587,186 “CMOS-Compatible Three-Dimensional Image Sensing Using Reduced Peak Energy”, 6,580,496 “Systems for CMOS-Compatible Three-Dimensional Image Sensing Using Quantum Efficiency Modulation”, 6,515,740 “Methods for CMOS-Compatible Three-Dimensional Image Sensing Using Quantum Efficiency Modulation”, 6,580,496 ‘Systems for CMOS-Compatible Three-Dimensional Image Sensing Using Quantum Efficiency Modulation”, 6,906,793 “Methods and Devices for Charge Management for Three-Dimensional Sensing”, 7,352,454 “Methods and Devices for Improved Charge Management for Three-Dimensional and Color Sensing”, and 7,464,351 “Method Enabling a Standard CMOS Fab to Produce an IC to Sense Three-Dimensional Information Using Augmented Rules Creating Mask Patterns Not Otherwise Expressible With Existing Fab Rules”.
FIG. 1A is based upon the above-referenced patents, e.g. the '186 patent, and depicts an exemplary phase-type TOF system. In FIG. 1A, exemplary phase-shift TOF depth imaging system 100 may be fabricated on an IC 110 that includes a two-dimensional array 130 of pixel detectors 140, which pixel detectors for purposes of the present inversion are preferably differential in operation. Preferably each of the pixel detectors 140 has dedicated circuitry 150 for processing detection charge output by the associated detector, and the term “pixel” 155 shall refer to an individual differential pixel detector 130 and its dedicated electronics 150. Because each pixel 155 may include dedicated electronics, pixel size tends to be somewhat large, perhaps 50 μm×50 μm. IC 110 preferably also includes a microprocessor or microcontroller unit 160, memory 170 (which preferably includes random access memory or RAM and read-only memory or ROM), a high speed distributable clock 180, and various computing and input/output (I/O) circuitry 190. Among other functions, controller unit 160 may perform distance to object and object velocity calculations.
Under control of microprocessor 160, optical energy source 120 is periodically energized by an exciter 115, and emits modulated optical energy toward an object target 20. Emitter 120 preferably is at least one LED or laser diode(s) emitting relatively low peak power (e.g., perhaps 1 W) periodic waveform, producing optical energy emissions of known frequency (perhaps a few dozen MHz) for a time period known as the shutter time (perhaps 10 ms). Typically emitter 120 operates in the near IR, with a wavelength of perhaps 800 nm. A lens 125 is commonly used to focus the emitted optical energy.
Some of the emitted optical energy (denoted Sout) will be reflected (denoted Sin) off the surface of target object 20. This reflected optical energy Sin will pass through an aperture field stop and lens, collectively 135, and will fall upon two-dimensional array 130 of pixel or photodetectors 140. When reflected optical energy Sin impinges upon photodetectors 140 in array 130, photons striking the photodetectors release photocharges that are converted into tiny amounts of detection current. For ease of explanation, incoming optical energy may be modeled as Sin=A·cos(ω·t+θ), where A is a brightness or intensity coefficient, ω·t represents the periodic modulation frequency, and θ is phase shift. As distance Z changes, phase shift θ changes, and FIGS. 1B and 1C depict a phase shift θ between emitted and detected signals. The phase shift θ data can be processed to yield desired Z depth information. Within array 130, pixel detection current can be integrated to accumulate a meaningful detection signal, used to form a depth image. In this fashion, TOF system 100 can capture and provide Z depth information at each pixel detector 140 in sensor array 130 for each frame of acquired data.
Signal detection within phase-type TOF systems such as system 100 is described more fully later herein with respect to FIG. 2B, but in brief, pixel detection information is captured at least two discrete phases, preferably 0° and 90°, and is processed to yield Z data.
System 100 yields a phase shift θ at distance Z due to time-of-flight given by:θ=2·ω·Z/C=2·(2·π·f)·Z/C  (1)where C is the speed of light, 300,000 Km/sec. From equation (1) above it follows that distance Z is given by:Z=θ·C/2·ω=θ·C/(2·2·f·π)  (2)
And when θ=2·π, the aliasing interval range (ZAIR) associated with modulation frequency f is given as:ZAIR=C/(2·f)  (3)
FIG. 2 is taken from U.S. Pat. No. 6,580,496 “Systems for CMOS-Compatible Three-Dimensional Image Sensing Using Quantum Efficiency Modulation and from U.S. Pat. No. 7,464,351 and is useful in understanding the concept of quantum efficiency modulation. FIG. 2 is not intended to be a component-by-component schematic, but rather a tool or metaphor to explain the underlying concepts. In simplified form, FIG. 2 depicts a quantum efficiency (QE) modulated pair of pixels 155-1, 155-N in array 130. The depletion width W of a photodiode 140 (or D) can be modulated using clock signals to vary the reverse bias across the photodiodes, preferably 180° out of phase. Thus, when diode D is biased to be sensitive, diode D′ is not, and vice versa. In this fashion, photodiode quantum efficiency (QE) is varied, which improves detection sensitivity. QE modulation techniques advantageously can accumulate detected signal charge, and are preferred over methods that attempt to directly measure high frequency, small magnitude detection photocurrent-generated signals. While the simplified representation of FIG. 2 suggests a one-terminal device, in reality the detectors are two-terminal devices (e.g., an output signal and a clock signal), and in preferred embodiments in which differential detectors are employed, four-terminal devices. Various quantum efficiency embodiments including fixed-phase and variable-phase are described in the cited patents. An advantage of quantum efficiency modulation is that phase and target object brightness information can be determined directly from the pixel detectors with relatively minimal additional circuitry.
But even employing quantum efficiency modulation, FIG. 2 suggests that providing every pixel with analog and digital components adds to the complexity of dedicated electronics 150, and thus to the IC chip area required to implement pixels 145. For example, in FIG. 2, each pixel requires analog and digital components including a differential amplifier, a capacitor, a phase delay unit, etc. Generally memory 170 includes software that can be executed by a processor, perhaps processor 160, to implement and control signals used in quantum efficiency modulation detecting.
Understandably the magnitude of the optical energy signals to be detected is small, and differential detection techniques are preferred to reduce the mal-effects of noise. FIG. 3A is taken from U.S. Pat. No. 7,464,351 “Method and System to Differentially Enhance Sensor Dynamic Range Using Enhanced Common Mode Reset”. FIG. 3A depicts an exemplary differential pixel 155, comprising a pixel detector PD and associated circuitry is shown in which during reset operation capacitors acquire exactly the same charge in each half of the pixel configuration. By adding exactly the same charge to each half of the configuration, common mode contribution is essentially removed and differential mode contribution is preserved. Such an approach offers several advantages. For example, extra resets do not affect the system operation, and the pixel detector may be reset even if it is not discharged. Further, capacitor or component mismatch has substantially no effect on the accuracy of the reset. In addition, it can be shown that common mode reset (CMR) generates no KT/C noise in the differential domain from capacitors CDA and CDB. The only resulting KT/C contribution appears in common mode where it is unimportant.
As analyzed and described in the '351 patent, reset operation for the embodiment of FIG. 3A advantageously centers the common mode about potential Vref. For ease of illustration, FIG. 3A does not depict QA, which is the sum of the charge on the top plate of capacitors CA and CDA, or QB, which is the sum of the charge on the top plate of capacitors CB and CDB. In operation, the configuration of FIG. 3A preserves the differential quantity QA−QB during the common mode reset operation, although the common mode quantity, (QA+Qs)/2, is changed at each reset. What occurs is that after a reset, the quantity (QA+QB)/2 is moved closer to some constant Qreset0. Thus in contrast to other reset approaches, additional resets substantially preserve the differential charge have no adverse impact in FIG. 3A as they simply move the operating point for (QA+QB)/2 even closer to Qreset0. Advantagously, the configuration of FIG. 3A does not require close matching of component values for capacitors CA, CB, CDA, and CDB, non-linearity of the capacitors does not affect performance.
In short, reset operation of the embodiment of FIG. 3A has the desired effect of centering the common mode about potential Vref. Relevant waveforms for FIG. 3A are shown in FIG. 3B and FIG. 3C. As a consequence, a reset can be applied without consideration of over-saturating or under-saturating the common mode for the pixel configuration. Thus in normal operation, reset can occur as often as desired without concern as to ill effects resulting from over or under saturation of the common mode.
Transistors TdisA and TdisB can be used as global shutters, thereby improving resilience to ambient light by stopping the effects of all light impinging on the differential pixel when the shutter is turned off. When TdisA and TdisB are off, capacitors Ca and Cb are decoupled from photodetectors PDDA and PDDB and therefore stop integrating the signal from PDDA and PDDB. If the output of the pixel is chosen to be top plate of capacitors CA and CB then the output of the pixel will be frozen after TdisA and TdisB are turned-off, thereby providing the function of a global shutter.
FIG. 4A depicts an embodiment using additional common mode reset circuitry 200 that improves differential loss while preserving relatively low KT/C noise characteristics. Within circuitry 200, operational amplifier 210 functions to remove differential detector signal charge from nodes OA, OB and to store the removed charge in an integration capacitor. With this functionality, the embodiment of FIG. 4A preserves the stored removed charge without substantial loss due to subsequent common mode reset cycles.
In practice, at least a substantial fraction (e.g., ≧50%) of the stored charge is removed for isolated storage on each so-called dump cycle. It will be appreciated that the system could function with less than 50% stored charge removal per cycle, however overall more differential charge will be lost during common mode reset operations. The result from saving at least a substantial fraction of the differential charge is improved dynamic range, improved retention of the desired differential detector signal, and improved common mode rejection. Components shown in FIG. 4A other than differential detector or pixel 140 may be designated as electronics 160, preferably dedicated to each pixel 155, and CMOS-implemented on the common IC 110. While improved performance is achieved, it is seen that the area requirements for pixel 155 increase due to the additional circuitry.
During an integration period T, operation of the embodiment exemplified by FIG. 4A involves a number n of common mode reset operations, and a number x of dumps (transfers-out) of the differential charge from capacitors CA, CB associated with each differential pixel detector into an active integration capacitor C220. Once dumped, the differential charge is stored in capacitor C220 and is not affected by subsequent common mode resets. More than one integration capacitor may be used, and within an integration period T, the number of dumps x may be less than or equal to or even greater than n.
During common mode reset operation, the differential detector signal charge is first read transferred into the integration capacitor C220 by turning-on dump transistors TdA, TdA′. So doing dumps charge from capacitor CA node OA and from capacitor CB node OB respectively into the non-inverting and inverting inputs of operational amplifier 210. Shutter transistors TshutA and TshutB remain open, which allows even the differential detector charge to be transferred. Subsequent common mode resets will have no effect on this safely stored-away differential detector and capacitor CA and CB charge. Next, shutter transistors TshutA and TshutB and dump transistors TdA, TdA′ are opened, and common mode reset is performed.
The embodiment of FIG. 4A limits charge loss to about 0.5%, e.g., about 99.5% of charge is retained. Furthermore, the 0.5% or so charge loss that occurs will be substantially independent of the number n of common mode rejection cycles, with no degradation to KT/C noise characteristics or removal of common mode by common mode reset.
Amplifier 210 provides a single-ended output signal (AMP OUT) that could be used to directly drive a bitline (BITLINE B) without use of a source follower such as TfB in FIG. 4A. Nonlinear effects of the source follower for bitline A are small because the voltage magnitude will be close to Vref3. Also depending upon how bitline readout is implemented, BITLINE A may be coupled directly to Vref3 instead of via a source follower for reasons of simplicity. Inclusion of a source follower introduces nonlinear effects, especially in the presence of a large differential signal when source followers TfA and TfB would be operating at different gate input voltages.
Components in sub-system 230 are optional but advantageously allow closed-loop gain of operational amplifier 210 to be varied by adding C240 to increase effective integration capacitance. Integration capacitance can be increased by judiciously enabling transistor switches in the feedback loop via control signals VGA1, VGA2, VGA3 and VGA4. This flexibility can advantageously vary amplifier 210 closed loop gain, and can be used to improve distance measurement resolution 62, while still avoiding amplifier saturation.
At the end of an integration period, the total accumulated charge in integration capacitor 220 (perhaps 40 fF) may be read-out in several ways. When the READ signal to the gate of transistor TrA is high (for the configuration shown), the signal present at the inverting input of operational amplifier 210 will be read-out to BITLINE A. Preferably simultaneously, the READ signal also turns-on transistor TrB such that BITLINE B reads-out the AMP OUT signal. What results is a differential signal across BITLINE A and BITLINE B that represents the correct voltage value stored on integration capacitor C220.
An alternate read-out method will now be described. Consider now the signal at the non-inverting input of operational amplifier 210. A high signal Cvref3 turns-on transistor Tref3, which couples a known reference voltage VREF3 to the non-inverting input of operational amplifier 210. As a result, a high READ signal to transistor TrB. reads-out the signal on BITLINE B. If necessary, BITLINE A may be read-out simultaneously to reduce the effects of noise on VREF3. The result is achieved by creating a differential value at the input of operational amplifier 210, wherein one of the differential values is VREF3.
It will be appreciated that some mismatch may exist between the values of storage capacitors CA, CB as well as between node parasitic capacitance, which mismatches can affect the final signal value of the first—described read-out method. It is understood that there will be parasitic capacitance at the non-inverting input of operational amplifier 210. Relative to a capacitor reset value of Vref, the AMP. The charge (with respect to a capacitor reset value of Vref) on this parasitic capacitance is substantially eliminated when the node is coupled to Vref3. This is what occurs in the second read-out method, but unfortunately a charge error is created whenever the initial amplifier input was not precisely Vref3. However effects of mismatch using the first read-out method and effects of charge error using the second read-out method can both be reduced by first bringing the voltage levels at both operational amplifier 210 inputs substantially to the initial reset value. The desired result can be accomplished by performing a series of common mode reset and charge dump operations before beginning the read-out sequence.
Alternately by reading from Bitline A a single ended value (denoted SBA), the error resulting from mismatch between Vref and voltages on the inputs to operational amplifier 210 can be compensated for mathematically. This is because for both read-out methods, there is a mathematical formula between the error and SBA. This mathematical formula is a function of SBA and integration capacitor C220, and either the capacitance mismatches (for the first read-out method) or the non-inverting operational amplifier positive terminal capacitance (for the second read-out method). Note that for the second read-out method the value SBA must be read-out before Vref3 is connected.
A combination of both read-out methods can be used, as follows. First the voltage on the two operational amplifier inputs is brought close to the reset voltage Vref3. Then SBA is read-out using either read-out method, and the remaining error is mathematically calibrated out. For economy of implementation, it is preferable to acquire SBA with relatively low accuracy. Thus in practice, SBA is read-out before the voltage on the operational amplifier inputs is brought close to reference voltage Vref3 via repeated common mode reset dump operations.
Before this series of common mode reset dump operations, magnitude of SBA relative to the reset voltage Vref3 will be fairly large, perhaps in the tens or hundreds of mV range. But after the series of common mode reset dump operations, this residual SBA voltage will be on the order of perhaps a few mV. Furthermore, this residual voltage will be a known fraction of the original SBA voltage before the series of common mode dump operations. Because this fraction is known a priori, by quantizing the larger quantity (magnitude of SBA before the reset operations), the smaller quantity (magnitude of SBA after the reset operations) can be known more accurately. The fraction can be determined empirically, or can be modeled taking into account relative values of CA, CB, and parasitic capacitance present at the non-inverting input of operational amplifier 210.
The addition of transistor switches connected to the DUMP B signal allows the differential detector system shown in FIG. 4A to function symmetrically with respect to “A” and “B” detector components. As a result, at some times the “A” and “B” components of differential detector 150 will be coupled to the non-inverting input and inverting, inputs, respectively, of operational amplifier 210, and at other times the capacitor couplings will be reversed. Within an integration period T, there may be several integration time slices defined. After each sub-integration time slice, one might decide to carry out a dump operation, a common mode reset operation or both. After each integration time slice, the roles of “A” and “B” within the differential detector may be alternated. This alternation can result from interchanging the clock signals for “A” and for “B”, or changing by 180° the phase of optical energy emitted by 120 (see FIG. 1A), which has the same effect. With such alteration, a differential signals is produced at the output of detector 155 that, to the first order, is the inverse of the differential signal at the previous sub-integration time slice.
Note that the DUMP B-related transistor switches couple operational amplifier 210 with the non-inverting and inverting input terminals switched with respect to DUMP A. As a result, the signal that accumulates on integration capacitor C220 accumulates in additive fashion. This feature advantageously substantially reduces many errors associated with offsets and the like, and reduces reliance upon 0°, 180° cancellation in different detection signal captures. This improvement follows because both 0° and 180° phases are used within a common capture (e.g., at a close time interval perhaps on the order of a mS or so) to cancel errors. Further, additional functionality results from the presence of operational amplifier 210, which may be used for multiple functions: to enhance common mode reset as noted above, and for pixel detector analog-to-digital conversation using techniques well known in the art. Other secondary uses of the operational amplifier can include dynamic range enhancement, 0°, 180° cancellation, 0°, 90° capture, and so on.
Some exemplary parameters for the embodiment of FIG. 4A not stated above will now be given. Capacitor C240 is nominally about half the value of integration capacitor 240, e.g., about 20 fF, where storage capacitors CA and CB are each about 60 fF. Exemplary fabrication data for transistors TfA, TfB are about 0.5μ/0.356μ, transistors TrA, TrB are about 1.5μ/0.6μ, transistors TrefA, TrefB, TresetA, TresetB are about 0.42μ/0.6μ, transistors TshutA, TshutB are about 0.42μ/0.6μ, and the four transistors associated with capacitors C220, C240 are each about 2μ/0.6μ.
FIG. 4B depicts various oscilloscope amplitude versus time traces for AMP IN, AMP OUT and DUMP A waveforms for a received detector light phase such that the AMP OUT signal increases with time. The integration period T in FIG. 4B is approximately 18 ms. The uppermost waveform is the AMP A or BITLINE B signal, which represents the accumulated differential between charge on capacitor CA and capacitor CB during the integration time T. It is seen that the AMP OUT signal approximates a stair-step waveform that increases every time DUMP A is turned on. The resetting of AMP IN and AMP OUT to the reference voltage preceding each reset occurring at events φF, is shown superimposed on the DUMP A reset signals. It is understood that when φF is active, high in this example, active reset signals are also present at φSW, φNOM, and so forth. In FIG. 48, waveforms just preceding events φF are read actions, for which the non-inverting operational amplifier input is coupled to Vref3. For ease of illustration, magnitude of Vref3 is intentionally shown as being different than magnitude of the reset voltage.
FIG. 5A is taken by U.S. Pat. No. 7,321,111 and depicts an embodiment of a differential pixel with improved differential dynamic range and signal/noise ratio. This embodiment provides common mode reset with restoration of common mode potential at the input of operational amplifier 210. Detector 140 is depicted as receiving a number of VBIAS and clock signals, but more or fewer such bias and clock signals can instead be used. Additional description regarding differential photodetectors may be found in U.S. Pat. No. 6,906,793 (2005) Methods and Devices for Charge Management for Three-Dimensional Sensing.
The embodiment of FIG. 5A seeks to avoid saturating even with relatively large amplitude differential signals, while also enhancing signal/noise ratio for the detection signal path. Saturation can be avoided by adding a fixed compensating offset (ΔV) to the differential signal voltage on capacitor CDSC whenever magnitude of the differential signal exceeds a predetermined maximum or minimum value. (If desired, the fixed compensating offset signal could of course be ΔQ, where Q is charge.). In FIG. 5A, circuitry 300 is used to implement the insertion, as required, of the fixed compensating offset (ΔV) into differential signal capacitor CDSC to avoid differential pixel saturation, even from relatively large amplitude differential signals. As such, offset ΔV is negative if the voltage on CDSC has become too positive, and the offset ΔV is positive if the voltage on CDSC has become too negative. In some embodiments, as indicated by FIG. 58, the accumulated charge voltage on the differential signal capacitor is checked synchronously, at which time ΔV is added, if needed. A count is kept of the number (N) of ΔV offsets that had to be added, and effective differential signal capacitor voltage is actual output voltage across the capacitor (Vo)+N·ΔV.
In other embodiments, as exemplified by FIG. 5C, reset of the integration capacitor voltage is asynchronous, and occurs whenever the voltage exceeds a predetermined maximum or minimum threshold. Again a count of the number (N) of resets is kept, and effective differential signal capacitor voltage is Vo+N·ΔV. These embodiments preserve the desired differential signal and prevent saturation of the differential pixel even when the differential signal is large in amplitude. Saturation due to common mode signal is prevented, preferably using embodiments described in U.S. Pat. No. 7,176,438.
Other embodiments of U.S. Pat. No. 6,321,111 describe how to dynamically vary the gain AG of pixel amplifier 270 to enhance detection signal/noise ratio by using a highest possible gain that still avoids saturation of the pixel electronics. A high amplifier gain (AG) advantageously reduces effective noise contribution downstream in the signal path by 1/AG. Gain of each such amplifier is variably controlled to adjust AG individually for each pixel as a function of its present signal value.
Within the array of differential pixels, each amplifier is first operated at maximum AG, and integration capacitor values are readout and stored in a row buffer. AG for each amplifier in the row is then incrementally decreased, and the row buffer is updated only for those amplifiers whose associated integration capacitor is not presently saturated. The above process is repeated until the value in the row buffer corresponds to the highest non-saturating gain for each amplifier associated with the row. The row buffer also records the value of the highest non-saturating gain for each amplifier associated with the row. At this juncture row buffer is readout, and the process is repeated for the next row in the array, and so on continuously. In this fashion amplifier values of AG are individually maximized, commensurate with avoiding overload or saturation of components downstream in the signal path. The desired result is enhanced signal/noise ratio. Alternative embodiments can, of course, increment rather than decrement amplifier gain, and cause the row buffer to latch the non-saturated gain value for each amplifier associated with a row.
In FIG. 5A, when accommodating for large differential dynamic range, let the differential charge first be converted to a single ended value and be collected in a differential signal capacitor CDSC. It is understood that the relationship between the detected differential photocurrent i, the capacitor CDSC, and the resultant voltage is given by i CDSCδV/δt.
As shown in FIG. 5B, at periodic intervals, e.g., at t1, t2, t3, . . . , magnitude of the charge voltage developed on capacitor CDSC is checked synchronously. If at the moment of check the voltage on CDSC exceeds a threshold, Vhigh or Vlow, then a compensating fixed amount of charge (denoted ΔV) is added to capacitor CDSC as a compensating offset. Thus if the accumulated voltage on CDSC becomes too positive, e.g., V>Vhigh, then an offset of −ΔV is added to capacitor CDSC, and if V becomes to negative, V<Vlow, then an offset of +ΔV is added to capacitor CDSC.
For example, in FIG. 5B at time t1, V>Vhigh and a negative offset ΔV is added to the capacitor voltage. At time t2, magnitude of the capacitor voltage does not exceed Vhigh or Vlow and no offset is added. However at time t3, the voltage is again too high and a negative offset ΔV is again introduced, and so on. The number (N) of resets is counted and at a given time, the effective voltage (Veffective), had no resetting occurred, is equal to Vout+nΔV. In this example, there were three resets (n=3), the Veffective=Vout+NΔV,=Vout+3ΔV. A diagram similar to FIG. 5B could be drawn for capacitor CDSC acquiring a negative charge, in which case a positive offset +ΔV would be added whenever the capacitor voltage goes below Vlow. If the effective capacitor saturation voltage is very high, an offset larger than Vhigh but preferably not larger than (Vhigh−Vlow) may be used to reduce the number of offsets N.
FIG. 5C depicts an alternative embodiment, again using the example of a capacitor CDSC acquiring a positive charge, in which the voltage on CDSC is reset asynchronously, whenever V>Vhigh. In this example, each reset adds −ΔV to the capacitor voltage, which returns the capacitor voltage to Vlow. Again the number N of resets is counted, and the effective capacitor voltage is given by Veffective=Vout+NΔV, or since n=4 in this example, Veffective=Vout+4ΔV. If the effective capacitor saturation voltage is very high, a negative reset offset, preferably not lower than Vlow (the low saturation voltage) may be used to reduce the number of resets N. Again a similar diagram may be drawn for the case of a capacitor CDSC accumulating a negative voltage.
The choice of implementing synchronous or asynchronous reset depends upon many factors. Generally, an asynchronous reset is more complex as each pixel must constantly monitor its differential signal capacitor voltage, and self generate control signals required to adjust the CDSC voltage. Further, these operations must be performed accurately in the presence of noise, as the other pixels are integrating and hence the modulation clocks are running. Further, if the reset count is not accumulated inside the pixel, the occurrence of resets may need to be communicated asynchronously, a difficult task when all pixels simultaneously reset. On the other hand a synchronous implementation requires more frequent resets as the pixels must be reset well before they saturate. Further, it must be ensured that the pixels have sufficient remaining margin such that they do not saturate before the next CDSC voltage check, which may not occur for a while. Also in synchronous implementations, each ΔV reset adjustment must be smaller as the CDSC voltage may be relatively far from saturation.
It was seen from equation (3) that changes in Z produce change in phase shift θ. However eventually the phase shift begins to repeat, e.g., θ=θ+2·π, etc., and distance Z is known modulo 2·π·C/2·ω)=C/2·f, where f is the modulation frequency. As such, an inherent ambiguity can exist between detected values of phase shift θ and distance Z in that if system 100 reports a distance Z1, in reality the actual distance may be any of ZN=Z1+N·C/2f, where N is an integer. The nature of this ambiguity may be better understood with reference to FIGS. 6A and 6B. In practice, multi-frequency methods are employed to disambiguate or dealias the phase shift data.
FIG. 6A is a mapping of detected phase θ versus distance Z for system 100. Assume that system 100 determines a phase angle θ′ for target object 20, where this phase information was acquired with a modulation frequency f1 of say 50 MHz. As shown by FIG. 6A, there are several distances, e.g., z1, z2, z4, z5, etc. that could be represented by this particular phase angle . . . but which is the correct distance? In FIG. 6A, ZAIR1 represents the Z distance aliasing interval range associated with z data acquired at frequency f1, and is the distance from z1 to z2, or z2 to z4, or z4 to z5, etc. These various z1, z2, z4, z5, distances are ambiguous and require disambiguation or dealiasing to identify the correct distance value.
It is desired to dealias the z data by increasing magnitude of the aliasing interval range ZAIR1. One prior art approach does this by increasing the ratio C/2f, which is to say, by decreasing the modulation frequency f, see equation (3). FIG. 6A also shows, in bold line, phase data acquired for a lower modulation frequency f2. In FIG. 6A, f2 is perhaps 20 MHz, in that the slope dθ/dz for the f2 waveform is less than about half the slope for the f1 waveform, where the slope dθ/dz is proportional to modulation frequency fm. FIG. 6B is a polar representation in which a vector, depicted as a line rotating counter-clockwise, rotates with velocity ω=dθ/dt=2πf. In prior art system 100, data is captured from pixel detectors at at least two discrete phases, e.g., 0° and 180°.
Thus in FIG. 6A, when the lower modulation frequency f2 is employed, the candidate distance values represented by phase θ′ are z3, z6, etc. As seen in FIG. 6A, the aliasing interval range ZAIR2 has advantageously increased from a short range ZAIR1 (associated with faster modulation frequency f1) to a greater range ZAIR2. The ratio of the aliasing interval range increase will be the ratio f2/f1. But acquiring phase data with lower modulation frequency f2 yields a Z value with less precision or resolution than if acquired with higher modulation frequency f1. This imprecision occurs because the slope of the curve for frequency f2 is about half the slope for modulation frequency f1. Thus errors in the measurement of phase acquired at f2 translate to greater errors in Z than errors in phase acquired at f1. For the same signal/noise ratio, errors in phases acquired at f1 and at f2 will be the same, but the corresponding uncertainty errors in Z use phase acquired at the lower f2 modulation frequency will be about twice as large for the representation of FIG. 6A. Thus, all things being equal, lowering the modulation frequency undesirably results in lower resolution (greater uncertainty) in accurately determining Z.
Thus while increasing the aliasing range interval is desired, doing so by decreasing the modulation frequency f is not desirable. This modulation frequency decrease approach to dealiasing is wasteful since lower modulation frequency means lower pixel sensor 140 accuracy per watt of illumination power from emitter 120 (see FIG. 1A). For example, a reduction of modulation frequency by a factor of 2.5, say from f=50 MHz to f=20 MHz, will advantageously increase the aliasing interval by the same factor, e.g., from 3 m to 7.5 m, but the penalty is a substantial (2.5)·(2.5)=6.25× increase in operating power to achieve similar uncertainty performance, assuming effects of ambient sunlight can be ignored.
Unfortunately, implementing dealiasing with prior art TOF systems 100 tends to further increase size of pixels 155, which is undesirable in that smaller rather than larger pixel sizes are desired. For a given size IC chip 110, it is understood that if individual pixels 155 could be reduced in size, array 130 could include a greater number of pixels with corresponding enhanced resolution. Alternatively, if the area of array 130 were reduced due to smaller sized pixels, then the area of IC 110 could be reduced, which would tend to reduce production costs and would tend to enhance yield.
From the various descriptions of FIGS. 1A-6B, it will be appreciated that implementing a feature rich time-of-flight system with high performance pixels, single-ended or preferably differential, requires providing analog and/or digital circuitry or functions on a per-pixel basis. So doing, however, increases the area on IC 110. FIG. 7A shows a portion of IC 110 and depicts the nature of the problem: individual pixels 155, each comprising a detector 140 and dedicated electronics 150, are too large, typically perhaps 50 μm×50 μm. This large pixel size results from the inclusion of numerous analog and/or digital circuitry or functions, as have been described, to implement pixel functionality and to improve pixel detection characteristics. What is needed is a configuration more like FIG. 7B, wherein individual detectors 140 may remain the same size, but the chip size needed for their dedicated electronics 150′ is reduced by intelligently removing from pixels 155 various common analog and/or digital circuits or functionality. The present invention provides such an architecture, which results in a small pixel size. As a result, more pixels can be accommodated by a given array area size on an IC chip, or for the same pixel density (numbers of rows×columns) as a prior art configuration, the array area size can be reduced. Preferably the resultant architecture not only provides smaller area pixels but also preserves (if not enhances) rich features desired in TOF systems, including dealiasing, manipulating RGB-Z data, including segmentation, up-sampling, and background substitution.